CZT Module Development

The baseline packaging approach for an imaging module and its external interface or connec-tion to the image plane is illustrated in Figure 1. A detector module consists of a patterned CZT substrate that has been PFC bonded to a ceramic (LTCC) substrate or multi chip module (MCM).

Figure 1 : Module and image plane interconnection
concepts. Top: integrated module (CZT sub-strate
PFC-bonded to LTCC substrate) and assembly onto
image plane. Bottom: underside of the module’s LTCC
substrate showing accommodation of passive com-
ponents, contact pads, and provi-sions for mounting
and alignment.

This modular concept has several important advantages.
-- It is compact and rugged and makes handling and mounting of the CZT detectors easy.
-- It helps to thermally isolate the CZT detector from the heat generating electronics.
-- It makes for a clean separation between the passive and active components of the detection system without the need for long leads that take up space and add capacitance and noise. This permits a clean separation of the detector and front end electronics development efforts.
-- It also allows the developers to evaluate various FEE implementations, from first breadboards to final ASICs, without requiring costly and risky disassembly and re-assembly operations.


The baseline FEE ASIC system concept is illustrated in the functional block diagram (Figure 2). In our proposed system concept there are 3 ASIC chips for each module mounted on the image plane board: a pixel ASIC, a strip ASIC and a common ADC.

Figure 2. FEE ASIC concept, functional block diagram.


Figure 3. Image plane concept. A 20 X20 array of imaging CZT modules.

The image plane concept is illustrated in Figures 1 and 3. The PCB segment shown in Figure 1, the module assembly drawing, represents a section of the image plane supporting one of many detector modules. In Figure 3we show an image plane board supporting a 20 X 20 CZT detector module array having 1024 cm² active area. The image plane is a large area, mechanically reinforced circuit board that supports an array of closely packed CZT detector modules. Using 0.5mm spacing between modules, a reasonable gap for facilitating assembly and disassembly, the estimated packing fraction is will be as high as 94%. The image plane board supports detector bias and the front end electronics ASICs and ADCs for pixel row and strip signal processing. These electronics are on the underside of the board. The PFC bonding and connector assembly interconnect technologies (Figure 1) provide good thermal isolation between the image plane board and the CZT. The cathode bias will be provided using a thin flexible circuit located between rows of modules (not shown). A thin light-tight cover is also necessary.